Exemplary embodiments relate generally to processing for computer chips within a computing environment, and more particularly to transferring data between chips.
In a computer system consisting of multiple central processors and cache chips, these chips must be interconnected so that data can be fetched, stored, and shared across the computer system. Conventionally, these command, response, and data transfers across the chip-to-chip interfaces have separate physical connections so that these operations (e.g., command, response, and data) do not interfere with each other. However, physical constraints may demand that these operations share a common physical link between chips. How these operations are multiplexed across the interface can have an impact on the overall performance of the system.
Strictly favoring data transfers over commands and responses that do not have data associated with them can cause a significant delay in getting the initial memory access command from the requesting central processor (also called central processor unit (CPU)) to memory, as the initial memory access command could be delayed many cycles at each chip-to-chip interface by ongoing data transfers. Alternatively, strictly favoring commands and responses without data over data transfer operations can cause fetch data for an earlier command to be unnecessarily delayed by newer commands. Some systems address this issue by strictly time-slicing access to the interface amongst the competing requestors. A three-cycle time slice scheme could allow command, response, and data elements to all be sent with maximum fairness. A strict time-slice scheme could have commands and responses share a slot, with data using another slot in a two-cycle time slice. Additionally, multiple data cycles could be incorporated into the sequence, as in a scheme which shares command and responses in 1 cycle, followed by 4 or 8 data cycles in a repeating sequence. However, in such schemes, data streams may be interrupted by empty command/data cycles, or streams of commands/responses may accumulate as they wait for their slot to become available on the interface, even when no data transfers are in progress.